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74LVC841A 10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State)
Product specification IC24 Data Handbook 1998 Jun 17
Philips Semiconductors
Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC841A
FEATURES
* 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic * Wide supply voltage range of 1.2 V to 3.6 V * In accordance with the JEDEC standard no. 8-1 A * Inputs accept voltages up to 5.5 V * CMOS low power consumption * Direct interface with TTL levels * Flow-through pin-out architecture
DESCRIPTION
The 74LVC841A is a low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. In 3-State operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment. The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The 74LVC841A consists of ten transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the ten latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr =tf 2.5 ns SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay Dn to Qn; LE to Qn Input capacitance Power dissipation capacitance per latch VI = GND to VCC1 CONDITIONS CL = 50 pF; VCC = 3.3 V TYPICAL 4.5 5.0 5.0 22 UNIT ns pF pF
NOTE: 1 CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES 24-Pin Plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LVC841A D 74LVC841A DB 74LVC841A PW NORTH AMERICA 74LVC841A D 74LVC841A DB 7LVC841APW DH PKG. DWG. # SOT137-1 SOT340-1 SOT355-1
PIN CONFIGURATION
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 1 2 3 4 5 6 7 8 9 10 11 24 23 22 21 20 19 18 17 16 15 14 13 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 LE
PIN DESCRIPTION
PIN NUMBER 1 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 SYMBOL OE D0 to D9 NAME AND FUNCTION Output enable input (active Low) Data inputs 3-state latch outputs Ground (0 V) Latch enable input (active HIGH) Positive supply voltage
23, 22, 21, 20, 19, Q0 to Q9 18, 17, 16, 15, 14 12 13 24 GND LE VCC
GND 12
SV01723
1998 Jun 17
2
853-2071 19589
Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC841A
LOGIC SYMBOL (IEEE/IEC)
13
LOGIC SYMBOL
13 1 C1 EN
2 3 4 5 6 7 8 9 10 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
LE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
23 22 21 3 20 4 19 5 18 6 17 7 16 8 15 9 14 10 11 15 14 16 17 18 19 20 21 22 2 1D 23
OE
Q9
1
SV01724
SV01725
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH 1 LE LE LE OE
LATCH 2 LE LE
LATCH 3 LE LE
LATCH 4 LE LE
LATCH 5 LE LE
LATCH 6 LE LE
LATCH 7 LE LE
LATCH 8 LE LE
LATCH 9 LE LE
LATCH 10 LE LE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
SV01726
FUNCTION TABLE for register An or Bn
INPUTS OPERATING MODES Enable and read register (transparent mode) Latch and read register latch register and disable outputs Hold OE L L L L H H L LE H H X X L Dn L H l h l h X INTERNAL LATCHES L H L H L H NC OUTPUTS Q0 TO Q9 L H L H Z Z NC
NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition X = don't care Z = high impedance OFF-state NC = no change
1998 Jun 17
3
Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC841A
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC input voltage range DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS LIMITS MIN 2.7 1.2 0 0 -40 0 0 MAX 3.6 3.6 5.5 VCC +85 20 10 UNIT V V V C ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI t 0 Note 2 VO uVCC or VO t 0 Note 2 VO = 0 to VCC CONDITIONS RATING -0.5 to +6.5 -50 -0.5 to +5.5 "50 -0.5 to VCC +0.5 "50 "100 -65 to +150 500 500 UNIT V mA V mA V mA mA C
mW
NOTES: 1 Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 17
4
Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC841A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER VCC = 1.2V VCC = 2.7 to 3.6V VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VOH HIGH level output voltage out ut VCC = 3.0V; VI = VIH or VIL; IO = -100A VCC = 3.0V; VI = VIH or VIL; IO = -18mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL II IOZ ICC ICC LOW level output voltage In ut Input leakage current 3-State output OFF-state current Quiescent supply current Additional quiescent supply current per input pin VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA VCC = 3 6V; VI = 5 5V or GND 3.6V; 5.5V VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 "0.1 "0 1 0.1 0.1 5 GND VCC*0.5 VCC*0.2 VCC*0.6 VCC*1.0 0.40 0.20 0.55 "5 "5 10 500 A A A A V VCC V TEST CONDITIONS Temp = -40C to +85C MIN VIH VIL HIGH level Input voltage In ut LOW level In ut voltage Input VCC 2.0 GND 0.8 TYP1 MAX V V UNIT
NOTE: 1 All typical values are at VCC = 3.3V and Tamb = 25C.
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500W; Tamb = -40_C to +85_C LIMITS SYMBOL PARAMETER Propagation delay Dn to Qn Propagation delay LE to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn LE pulse width, HIGH Set-up time Dn to LE Hold time Dn to LE WAVEFORM MIN tPHL/tPLH tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tw tsu th Figures 1, 5 Figures 2, 5 Figures 3, 5 Figures 3, 5 Figure 4 Figure 4 Figure 4 1.5 1.5 1.5 1.5 2.0 2.0 1.0 VCC = 3.3V 0.3V TYP1 4.5 4.9 5.4 3.8 0.7 0.5 -0.5 MAX 6.7 7.6 7.9 5.9 - - - VCC = 2.7V MIN 1.5 1.5 1.5 1.5 2.0 2.0 1.0 MAX 7.5 8.6 8.9 6.9 ns ns ns ns ns ns ns UNIT
NOTE: 1 All typical values are at VCC = 3.3V and Tamb = 25C.
1998 Jun 17
5
Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC841A
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V VM = 0.5 V x VCC at VCC < 2.7 V VM = 1.5 V at VCC = 3.0 V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3 V at VCC 2.7 V VX = VOL + 0.1 x VCC at VCC < 2.7 V VY = VOH - 0.3 V at VCC 2.7 V VY = VOH - 0.1 x VCC at VCC < 2.7 V
VI Dn Input GND tPHL VOH Qn Output VOL VM tPLH VM VI D n INPUT GND VM th t su VI LE INPUT GND VM t su th
SV01730
Figure 4. Data set-up and hold times for the Dn input to LE input. Note to Figure 4: The shaded areas indicate when the input is permitted to change for predictable output performance
TEST CIRCUIT
VCC S1
SV01727
VI D.U.T. RT CL 50pF 500 VO 500
2 x VCC Open GND
Figure 1. Input (Dn) to output (Qn) propagation delays.
VI LE INPUT GND tW t PHL VOH Q n OUTPUT VOL VM t PLH VM PULSE GENERATOR
Test VCC t 2.7V 2.7V - 3.6V VI VCC 2.7V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 2 x VCC GND
SV01729
SY00003
Figure 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays.
VI OE INPUT GND tPLZ VCC Qn OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ VOH Qn OUTPUT HIGH-to-OFF OFF-to-HIGH GND VY VM VM VX tPZH tPZL VM
Figure 5. Load circuitry for switching times.
outputs enabled
outputs disabled
outputs enabled
SV01728
Figure 3. 3-State enable and disable times.
1998 Jun 17
6
Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC841A
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
1998 Jun 17
7
Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC841A
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
1998 Jun 17
8
Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC841A
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
1998 Jun 17
9
Philips Semiconductors
Product specification
10-bit transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC841A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 06-98 9397-750-04522
Philips Semiconductors
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